Various storage systems comprise multiple memory devices that connect to a controller via some bus interface or link. The write throughput of the system, i.e., the amount of data that can be stored during a unit of time, is a critical performance measure of the storage system. Write throughput can be measured, for example, in Mbytes per second.
Methods for scheduling write commands to multiple memory devices are known in the art. For example, U.S. Pat. No. 8,441,869, whose disclosure is incorporated herein by reference, describes data storage systems including a plurality of memories and a control circuit coupled to the plurality of memories by a common channel. The control circuit is configured to sequentially transfer respective units of data to respective memories within each of a plurality of predetermined groups of the plurality of memories over the common channel and to transition from transferring units of data to a first one of the groups to transferring units of data to a second one of the groups based on an attribute of the units of data. The attribute may be related to a programming time associated with a unit of data. For example, the attribute may include a bit-significance of the unit of data.
U.S. Pat. No. 9,153,324, whose disclosure is incorporated herein by references, describes a die assignment scheme that assigns data, in the order it is received, to multiple memory dies with some randomness. Randomization events, such as skipping dies or reversing direction, occur at intervals, with a deterministic assignment scheme used between randomization events. Intervals between randomization events may be of random length, or of fixed length.